1. Field of the Invention
The present invention relates to an output circuit and a data driver of a liquid crystal display device employing the output circuit.
2. Description of the Related Art
Currently, in the field of display devices, active matrix liquid crystal display devices are in the mainstream. The liquid crystal display device is widely used for most display devices, for example, from personal digital assistants such as smartphones or tablet terminals to high-resolution large-screen devices such as 4K or 2K monitors or TVs.
The data driver for driving a display panel is required of outputting highly accurate gradation voltages as well as driving data lines at high speeds in order to support displaying high-quality images or displaying moving images. Thus, the output circuit of a data driver is required of a high driving capability in order to charge and discharge the data line capacity of the display panel at high speeds. Furthermore, in order to achieve a good display quality, also required are the symmetry and uniformity of the gradient of a drive waveform at the time of charging and discharging the data lines, that is, the slew rate of the output amplifier circuit of the data driver.
Furthermore, in the liquid crystal display, the voltage level of a voltage applied to the liquid crystal controls the transmittance according to the gradation. Then, in order to prevent deterioration in the liquid crystal, the polarity of the voltage to be applied to the liquid crystal has to be varied at certain intervals. In general, the data driver employs such a drive scheme as to drive data lines by switching at certain intervals between a positive gradation voltage and a negative gradation voltage with respect to a constant common voltage. Thus, the data driver requires a supply voltage (maximum about 20 V) which is about two times greater than the applied voltage range of the liquid crystal.
Recently, in order to reduce power consumption, the drive scheme for the data driver transitions from the dot inversion driving by which the positive and negative polarities are switched for each data period to the column inversion driving by which the positive and negative polarities are switched for each one frame period (one-screen rewriting period). The data driver for the column inversion driving employs, as an output circuit, a half VDD amplifier for outputting positive and negative gradation voltages using three power supplies, i.e., an upper level power supply voltage VDD, a middle level power supply voltage VML (around the common voltage), and a low level power supply voltage VSS (=GND).
Known as the half VDD amplifier for the column inversion driving is an output amplifier of a two-output configuration which is provided with drive power supplies for the respective positive/negative polarity dynamic ranges (for example, Japanese Patent Application Laid-Open No. 2009-244830).
In the two-output amplifier, the supply voltage range of the differential input stage circuit is full VDD (=VDD−VSS), and the respective supply voltage ranges of the two-output stage circuit are the positive half VDD (=VDD−VML) and the negative half VDD (=VMH−VSS) (for example, VML=VMH=VDD/2). Then, the two output stage circuits are configured to be switchable depending on the voltage polarity of an input voltage of the differential input stage circuit.
This is to prevent degradation in display quality by sharing the differential input stage circuit, which determines the variation in offset voltage, at the time of output of positive voltages and at the time of output of negative voltages because variations in the offset voltage of the positive and negative output voltages (i.e., errors from the expectation value of output voltages) may lead to deterioration in display quality.
However, for high-speed driving (the column inversion driving) of heavy capacitive loads, for example, in a charging operation, with an initial state in which a positive voltage around the middle level power supply voltage VML is input as a positive input voltage of the differential input stage circuit, a positive voltage around high level power supply voltage VDD in the first data period is input. At this time, the gate voltages of Pch and Nch output stage transistors in the output stage circuit may be significantly deviated from a positive voltage range in a transient manner and thereby reduced to a potential lower than the middle level power supply voltage VML. At this stage, the first data period is ended, and then when the positive input voltage is changed to a lower voltage (for example, around the middle level power supply voltage VML) in the next second data period, the process will not be switched to a discharging operation unless the gate voltages of the Pch and Nch output stage transistors exceed the middle level power supply voltage VML and rise to a potential at which the Nch output stage transistor is turned on. Thus, in the second data period, a considerable output signal delay may be produced, thereby causing degradation in display quality.
Likewise, in the discharging operation, in the initial state in which a negative voltage around the middle level power supply voltage VMH is input as a negative input voltage of the differential input stage circuit, a negative voltage around the low level power supply voltage VSS is input in the first data period. At this time, the gate voltages of the Pch and Nch output stage transistors in the output stage circuit may be significantly deviated from a negative voltage range in a transient manner and thereby raised to a potential higher than the middle level power supply voltage VMH. At this stage, the first data period is ended, and then when the negative input voltage is changed to a higher voltage (for example, around the middle level power supply voltage VMH) in the next second data period, the process will not be switched to a charging operation unless the gate voltages of the Pch and Nch output stages exceed the middle level power supply voltage VMH and are reduced to a potential at which the Pch output stage transistor is turned on. Thus, in the second data period, a significant output signal delay (the asymmetry or non-uniformity of output waveforms) may be produced, leading to degradation in display quality.
In this context, such an output circuit was conceived in which the differential amplifier circuit, to which a positive voltage is input, is provided with a control transistor, which is turned on or off when receiving a bias signal, between a low potential current mirror circuit and the gate of the Nch output stage transistor. In this output circuit, the control transistor is turned off when the gate of the Nch output stage transistor is to be further reduced from the middle level power supply voltage VML, thereby preventing the gate voltage of the output stage transistor from being reduced below the middle level power supply voltage (for example, FIG. 1 in Japanese Patent Application Laid-Open No. 2012-39345). Likewise, such an output circuit was conceived in which the differential amplifier circuit, to which a negative voltage is input, is provided with a control transistor, which is turned on or off when receiving a bias signal, between a high potential current mirror circuit and the gate of the Pch output stage transistor. In this output circuit, the control transistor is turned off when the gate of the Pch output stage transistor is to be further raised from the middle level power supply voltage VMH, thereby preventing the gate voltage of the output stage transistor from being raised above the middle level power supply voltage (for example, FIG. 2 in Japanese Patent Application Laid-Open No. 2012-39345).
In the output circuit in Japanese Patent Application Laid-Open No. 2012-39345 above, a clamping bias signal to be supplied to the gate of the control transistor is additionally required, thus leading to an increase in bias lines. Furthermore, in the configuration of Japanese Patent Application Laid-Open No. 2009-244830 above, a similar clamp element can be added to the respective positive and negative output amplification stages so as to prevent the gate voltage of the positive output stage transistor from deviating from a positive side power supply voltage range and prevent the gate voltage of the negative output stage transistor from deviating from a negative supply voltage range, thereby reducing output signal delay. However, in this case, an additional clamping bias signal is also required, leading to an increase in bias lines.
Since the bias lines of a data driver for display are typically to be wired in common from a bias circuit at the center of a chip to a plurality of output circuits, an increased number of bias lines may be more easily subjected to the influence of noise caused, for example, by coupling with crossing conductor traces, thereby leading to an increase in the risk of malfunction. Furthermore, from the viewpoint of ease of design, a less number of bias lines may be preferable, and the number of conductor traces is required to be reduced.